Supermicro X8DTN+ Manual de usuario descargar pdf (Pagina 17)

Chapter 1: Introduction

1-9

1-3 Processor and Chipset Overview

Built upon the functionality and the capability of the 5500 Series Processor

platform, the X8DTN+ motherboard provides the performance and feature set

required for dual-processor-based high-end systems with conﬁ guration optimized

for intensive application and high-end server platforms. The 5500 Series Proces-

sor platform consists of the 5500 Series (LGA 1366) processor, the 5520 (North

Bridge), and the ICH10R (South Bridge). With the Intel QuickPath Interconnect

(QPI) controller built in, the 5500 Series Processor platform is the ﬁ rst dual-

processing platform to offer the next generation point-to-point system interconnect

interface that replaces the current Front Side Bus Technology and substantially

enhances system performance by utilizing serial link interconnections, allowing

for increased bandwidth and scalability.

The 5520 connects to each processor through an independent QuickPath Inter-

connect link. Each link consists of 20 pairs of uni-directional differential lanes for

transmission and receiving in addition to a differential forwarded clock. A full-width

QPI link pair provides 84 signals. Each processor supports two QuickPath link,

one going to the other processor and the other to the 5520.

The 5520 supports up to 36 PCI Express Gen2 lanes, peer-to-peer read and write

transactions. The ICH10R supports up to 6 PCI-Express ports, six SATA ports

and 10 USB connections.

In addition, the 5500 Series Processor platform also offers a wide range of

RAS (Reliability, Availability and Serviceability) features. These features include

memory interface ECC, x4/x8 Single Device Data Correction (SDDC), Cyclic Re-

dundancy Check (CRC), parity protection, out-of-band register access via SMBus,

memory mirroring, memory sparing, and Hot-plug support on the PCI-Express

Interface.

The Main Features of the 5500 Series Processor and the

5520 Chipset

Four processor cores in each processor with 8MB shared cache among cores•

Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer •

rate in each direction

Virtualization Technology, Integrated Management Engine supported

•

Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and •

Concurrent bi-directional trafﬁ c

Error detection via CRC and Error correction via Link level retry

•

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 94 95

Sin comentarios

Supermicro X8DTN+ Manual de usuario Pagina 17